In order to further attain high integration and high speed operation of a large scale integrated circuit (LSI), miniaturization of a metal-oxide semiconductor field effect transistor (MOSFET), which is a basic component thereof is promoted. This miniaturization is performed so as to keep the MOSFET device in a normal operation in accordance with a scaling rule in such a manner that three dimensional sizes of the device are reduced at the same time.
Important requirements for MOSFET scaling include, in addition to miniaturization of the tree dimensional actual sizes, reductions of a potential difference in a lateral direction crossing a source and a drain of a field effect transistor (FET) and a potential difference in a vertical direction viewed from a gate electrode at the same time, to thereby keep a constant field intensity itself inside the device. As the result of performing the above-mentioned scaling, reduction of a power voltage (Vdd) works effectively to reduce an operation voltage of the MOSFET, attaining the higher performance of the LSI year by year.
Meanwhile, as an adverse effect of the Vdd reduction, there arises a need to reduce a threshold voltage (Vth) to secure an operation current (Ion). For this reason, in device generations having a channel length of 1μ or less, the reduction of the threshold voltage causes a reason to markedly increase a leak current (sub-threshold leak current: Isb) flowing the source/drain when the FET is an off state. As a result, a merit of low power consumption in the LSI by virtue of the reduction of the Vdd is impaired.
In view of the above-mentioned backgrounds, there is investigated a technology to suppress the leak current by controlling not only the gate voltage but also a substrate bias (for example, refer to, T. Hiramoto, et al., Jpn. J. Appl. Phys., Vol. 40 (2001) 2854. (Non-patent Document 1)). It is found that a surface potential of a channel, which is essentially controlled by the gate electrode, is auxiliary controlled by applying a substrate bias, thereby being capable of controlling the Isb effectively.
In a case of a p-type MOSFET, for example, by applying a positive substrate bias thereto, the surface potential of the channel can be modulated into a positive direction. Therefore, it is required to apply a negative voltage more largely to the gate voltage to attain a formation of a reverse state at the channel portion. As a result, the threshold voltage becomes high. In a case of an n-type MOSFET, a reverse relation holds true in terms of voltage.
However, in the above-mentioned MOSFET, which requires a particularly high Ion, it is required to reduce an injection amount to the channel portion to lower the threshold voltage. For this reason, in a case where an electric field which is opposite to that of the gate electrode is applied to a substrate, a width of a depletion layer formed below the channel becomes wider, the above-mentioned substrate bias effect (hereinafter, abbreviated as “γ”) becomes smaller as the miniaturization of the MOSFET advances.
Because it is required to increase an impurity concentration in a well to shorten the width of the depletion layer, there is generally employed a retrograde structure in which the impurity profile becomes higher as a depth in the substrate becomes deeper. However, when employing the retrograde structure, in the MOSFET of submicron generations, it is conceivable that the impurity concentration in a junction surface of the source/drain (hereinafter, source/drain may sometimes be referred to as “SD”) may inevitably increase, or a junction capacitance or a junction leak current increases due to a crystal defect generated at the junction portion, thereby being not preferred in view of the MOSFET operation.
Besides, Japanese Unexamined Patent Application Publication (JP-A) No. 2001-68672 (Patent Document 1) describes a method involving injecting impurities from right above the channel portion while opening the gate electrode portion only, to improve device characteristics by varying the impurity concentration below the channel.
However, to improve the γ, it is required to form high impurity portion in the vicinity directly below the channel, so there was a problem in that it is difficult to form such an acute reverse profile without affecting the threshold voltage. Further, there is a fear of degrading the performance of the FET, because the crystal defects may be introduced into the channel portion as the injection of ion.
Besides, Japanese Unexamined Patent Application Publication (JP-A) No. Hei 11-233769 (Patent Document 2) discloses a method involving injecting, after the formation of the gate electrode, from <110> axis direction which causes channeling at the time of ion injection, to thereby inject the ion at a deep portion below the channel formation region. However, in a case of utilizing the channeling at the time of ion injection, if a slight shift occurs in the injection direction, the injection profile largely varies, resulting in being unable of providing a MOSFET as a product having stable characteristics. In addition, there was a great problem when manufacturing, because the injection is limited to the <110> direction, it is required to perform the ion injections each independently depending on the direction of the transistor integrated on the wafer.